The present invention relates to a method for fabricating a DRAM cell having a trench capacitor.
DRAM memories fall back upon the pulsed operation of SRAM memories. The capacitances always present in the memory cell, e.g. the gate capacitance, are used to retain its state for a certain time. This principle allows significant simplification of the memory cell, so that power consumption and area requirement decrease: the packing density of the memory increases. In order to increase the packing density even further, it is endeavored to further reduce the area requirement of DRAM cells. In this case, the aim is to keep the storage capacitance large and the stray capacitances of the bit and word lines as small as possible. At the same time, the fabrication methods for a DRAM chip should be as simple as possible.
U.S. Pat. No. 4,797,373 describes a DRAM memory cell and a fabrication method for a DRAM memory cell using trench technology. In the DRAM cell according to this prior art, the cell comprises a field-effect transistor and a storage capacitor, both the transistor and the capacitor being fabricated in a trench in a substrate. The source of the transistor, the channel and the drain and also one capacitor area are arranged essentially vertically in the side walls of the bulk substrate, and the gate and the other capacitor area are arranged in two regions of a material which is inserted into the trench and is insulated from the bulk by an insulator layer. In other words, the storage capacitor and the selection transistor are practically arranged one above the other under the crossover area of the bit and word lines.
The method for fabricating a DRAM memory cell having a storage capacitance and a selection transistor according to the above prior art essentially comprises the following steps:
etching of a trench in a substrate of a first conductivity type;
coating of the side areas of the trench with a first thin insulator layer;
filling of the lined trench up to a predetermined height with conductive material of a second conductivity type;
removal of the uncovered insulator layer including edge regions of the insulator layer between the conductive material and the substrate;
deposition of a conductive material in the edge regions;
diffusion of dopant from the conductive material through the edge regions into the substrate surrounding the trench, thereby producing, at the level of the edge regions in the substrate, weakly doped regions of the second conductivity type, which serve as the source of the selection transistor;
formation of a drain region in the substrate adjacent to the upper part of the trench;
formation of a gate insulator layer in the upper part of the trench; and
filling of the rest of the trench with a conductive material serving as gate.
In this case, the substrate has a highly doped lower zone and a less highly doped upper zone, the source of the selection transistor being situated in the more weakly doped upper zone.
In this case, six essential steps concern the fabrication of the storage capacitance and of the gate of the selection transistor, and the remaining three steps exclusively concern the selection transistor. The method steps involve a significant difficulty in respect of carrying out the etching at the predetermined edge regions in a controlled manner, so that the dimensions of the predetermined edge regions are reproducible.
It is an object of the present invention to specify a fabrication method for a DRAM cell which is simple to carry out, has a high yield, permits a high packing density of the DRAM cells and reduces the interconnect capacitances.
This object is achieved by means of a method for fabricating a DRAM cell according to claim 1. The subclaims relate to preferred developments of the invention.
The invention is based on the idea of fabricating the DRAM cell by a method which has similar steps to the SOI method, namely in which a monocrystalline silicon layer is arranged on a support. Whereas in the SOI method the support is an insulator (SOI=silicon on insulator), in the xe2x80x9cquasi-SOIxe2x80x9d method according to the invention the monocrystalline silicon layer is produced as a second zone on a further silicon layer, which constitutes a first zone. The storage capacitance of the DRAM cell is produced in the first zone, and the selection transistor is produced in a silicon pillar in the second, upper zone. The invention""s method for fabricating a DRAM memory cell thus has the steps of: producing a first trench in a first zone of a first conductivity type, coating the surface of the first trench with a first insulator layer and filling the first trench with a conductive material of a second conductivity type, the first zone and the conductive material in the first trench being highly doped;
arranging a second zone of the first conductivity type on the first zone, so that the first trench is covered; producing a region of the second conductivity type in the second zone by diffusion of dopant from the conductive material in the first trench;
etching adjacent regions next to the first trench, so that semiconductor material is removed proceeding from the surface right into the second zone;
filling the adjacent regions with an insulator material, so that an insulator is produced between adjacent first trenches;
producing bit lines made of conductive material of the second conductivity type and drain zones for selection transistors;
producing the selection transistor in a second trench in the second zone above the first trench in the first zone; and
producing word lines on the uncovered surface of the second zone.
Preferably, arranging the second zone on the first zone comprises the steps of xe2x80x9cDirect Wafer Bondingxe2x80x9d of the second zone on the first zone and thinning of the second zone to a predetermined thickness. This makes it possible to arrange the two differently doped zones on top of one another in a simple step. The thinning process can be effected by etching or by grinding and subsequent polishing.
In a preferred development of the method, the process of coating the surface of the first trench with an insulator layer is in each case effected by oxidation.
In particular, the adjacent regions of the first trench in which semiconductor material has been removed can be filled by a thick oxide. This is possible in a simple work step.
One advantage of the invention is that fewer masks are required during fabrication, i.e. only five masks in the exemplary embodiment compared with six in the comparable prior art. A further advantage is that the parasitic capacitances of the DRAM memory cell remain smaller with the method according to the invention than in the methods according to the prior art.